Subject: Electronic System Level Design (17 - EM458)


Basic Information

CategoryScientific-professional
Scientific or art field:Electronics
InterdisciplinaryNo
ECTS6
Course specification

Course is active from 20.10.2012..


Precondition courses

Course idMandatoryMandatory
Design of Complex Digital SystemsYesNo
Acquiring knowledge about the system level design techniques of embedded systems. Learning how to use standard languages, techniques and methodologies, as well as tools for the successful design of embeded system at the system level.
- ability to develop a system level model of the embedded system using some of the standard System Level languages - ability to profile and optimize system level performance based on the design goals - ability to verify developed embedded system at the system level
Methodology of System-Level design. Models of computation used at system level: finite state machines (FSMs), dataflow, process networks. System-Level design languages: MATLAB, SystemC, SpecC. System-Level modeling: transaction-level modeling (TLM) for communication, processor and RTOS modeling. Specification, profiling and analysis of HW/SW systems. Codesign of hardware and software. System-Level design methodologies and tools for: partitioning, scheduling and communication synthesis. High Level synthesis. System-Level design of low power systems. Verification at the System-Level: verification based on simulation, verification based on formal methods, coverification of hardware and software.
Lectures. Computer labs. Consultations.
AuthorsNameYearPublisherLanguage
D. D. Gajski, S. Abdi, A. Gerstlauer, G. SchirnerEmbedded System Design: Modeling, Synthesis, Verification2009Springer VerlagEnglish
M. Fujita, I. Ghosh, M. PrasadVerification Techniques for System Level Design2008Morgan KaufmannEnglish
B. Bailey, G. Martin, A. PizialiESL Design and Verification - A Prescription for Electronic System Level Methodology2007Morgan KaufmannEnglish
Course activity Pre-examination ObligationsNumber of points
Complex exercisesYesYes20.00
ProjectYesYes50.00
Theoretical part of the examNoYes30.00
Name and surnameForm of classes
Missing picture!

Vranjković Vuk
Associate Professor

Lectures
Missing picture!

Struharik Rastislav
Full Professor

Lectures
Missing picture!

Radovanović Boris
Assistant - Master

Laboratory classes